IMX7ULPCEC datasheet(97/118 Pages) NXP

97 / 118 page

9.1.3 14 x 14 mm power supply and functional contact

assignments

The following table shows the power supply contact assignments for the 14 × 14 mm

package.

Table 62. 14 x 14 mm power supply contact assignments

Supply Name

14x14 mm VP Package Ball

Position

Remarks

DDR_ODT

AA22

DDR on-die termination

DDR_VREF0

H23

DDR voltage reference input. Connect to a voltage

source that is 50% of VDD_DDR.

DDR_VREF1

Y23

DDR voltage reference input. Connect to a voltage

source that is 50% of VDD_DDR.

DDR_ZQ0

AG24

Connect DDR_ZQ0 to an external 240Ω 1% resistor

to Vss. This is a reference used during DDR output

buffer driver calibration.

TESTCLK_N

AA8

Test function for NXP use only. This output must

remain unconnected.

TESTCLK_P

AB8

Test function for NXP use only. This output must

remain unconnected.

USB0_VBUS

USB0 VBUS detection

VDD_ANA18

AB11

ADC analog and IO 1.8V supply input

VDD_ANA33

AA12

ADC analog and IO 3.3V supply input

VDD_DDR

H22, J21, M22, N21, T21, U22, Y21 DDR I/O supply input

VDD_DIG0

V16, V17

M4 domain core and logic supply input

VDD_DIG1

K11, K12, K13, K15, K16, K17, L10,

L14, L18, M10, M18, N10, N18,

P11, P17, R10, R18, T18, U18

A7 domain core and logic supply input

VDD_DSI11

MIPI DSI 1.1V supply input

VDD_DSI18

MIPI DSI 1.8V supply input

VDD_HSIC

HSIC 1.2V supply input

VDD_PLL18

PLL analog supply input

VDD_PMC11_DIG0_CAP

U14, V15

M4 domain LDO supply output

VDD_PMC11_DIG1_CAP

T10, U10

A7 domain LDO supply output

VDD_PMC12_DIG1

AB4, AC4

A7 domain LDO and internal memory LDO supply

input

VDD_PMC18

AB3

M4/A7 PMC and PMC IO supply input

VDD_PMC18_DIG0

V11, V12, V13

M4 domain LDO and internal memory LDO supply

input

VDD_PTA

AA15, AA19

GPIO Port A supply input

VDD_PTB

AA11, AD6

GPIO Port B supply input

Table continues on the next page...

Package information and contact assignments

i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019

NXP Semiconductors

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