IMX7ULPCEC datasheet(64/118 Pages) NXP

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7.1.3 Flexbus switching specifications

All processor bus timings are synchronous; input setup/hold and output delay are given

in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency

may be the same as the internal system bus frequency or an integer divider of that

frequency.

The following timing parameters indicate when data is latched or driven onto the

external bus, relative to the Flexbus output clock (FB_CLK). All other timing

relationships can be derived from these values.

Table 35. Flexbus switching specifications

Num

Parameter

Min.

Max.

Unit

Notes

Frequency of operation

• HSRUN mode

• Normal RUN mode

—

MHz

FB1

Clock period

• HSRUN mode

• Normal RUN mode

15.0

—

FB2

Address, data, and control output valid

—

13.0

FB3

Address, data, and control output hold

1.0

—

FB4

Data input setup

8.5

—

FB5

Data input hold

0.0

—

1. Specification is valid for all FB_AD[31:0], FB_BE, FB_CSn_B, FB_OE_B, FB_RW_B, FB_TBST_B, FB_TSIZ[1:0],

FB_ALE, and FB_TS_B.

2. Specification is valid for all FB_AD[31:0].

Specifications—application domain

i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019

NXP Semiconductors

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