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CEC1712 bảng dữ liệu(PDF) 12 Page - Microchip Technology

tên linh kiện CEC1712
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nhà sản xuất  MICROCHIP [Microchip Technology]
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CEC1712 bảng dữ liệu(HTML) 12 Page - Microchip Technology

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CEC1712
DS00003416C-page 12
 2020-2021 Microchip Technology Inc.
Note:
GPIO055/PWM2/SHD_CS0# should be pulled up for proper boot up of the chip.
2.4
Pin Multiplexing
2.4.1
DEFAULT STATE
The default state for analog pins is Input. The default state for all pins that default to a GPIO function is input/output/inter-
rupt disabled. The default state for pins that differ is shown in the Section 3.5, "GPIO Register Assignments". Entries for
the Default State column are
• O2ma-Low:
Push-Pull output, Slow slew rate, 2ma drive strength, grounded
• O2ma-High
Push-Pull output, Slow slew rate, 2ma drive strength, high output
• PU
Input, with pull-up resistor enabled
2.4.2
POWER RAIL
The Power Rail column defines the power pin that provides I/O power for the signal pin.
D7
GPIO156/LED0
B9
GPIO157/LED1
C5
GPIO045/PWM2_ALT/ICT14
A6
GPIO165/32KHZ_IN/CTOUT0
C2
GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX
B6
GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX
A7
GPIO147/I2C15_SDA/JTAG_CLK
B3
GPIO150/I2C15_SCL/JTAG_TMS
E7
GPIO143/I2C04_SDA/UART0_CTS#
D6
GPIO144/I2C04_SCL/UART0_RTS#
A8
GPIO004/I2C00_SCL
B5
GPIO003/I2C00_SDA
A5
VCI_IN3#/GPIO000
B4
VCI_IN0#/GPIO163
B1
BGPO0/GPIO253
A1
VCI_OUT/GPIO250
A4
XTAL1
A2
XTAL2
D4
VSS_ANALOG
C1
VTR_PLL
D5
VBAT
E4
VSS
E1
VTR_REG
E3
VREF_ADC
F7
VSS
G6
VTR1
F4
VTR_ANALOG
F1
VR_CAP
G5
VTR2
J1
VSS_ADC
Ball map
Signal



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