CEC1712 datasheet(83/338 Pages) MICROCHIP

83 / 338 page

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DS00003416C-page 83

CEC1712

The EC operates on the model of a single 32-bit addressing space of byte addresses (4Gbytes, Von Neumann archi-

tecture) with Little-Endian byte ordering. On the basis of an internal decoder (part of the Bus Matrix shown in Figure 5-

1), it routes Read/Write/Fetch accesses to one of three external interfaces, or in some cases internally (shown as the

PPB interface).

The EC executes instructions out of closely-coupled memory via the ICode Interface. Data accesses to closely-coupled

memory are handled via the DCode Interface. The EC accesses the rest of the on-chip address space via the System

AHB-Lite interface. The Debugger program in the host can probe the EC and all EC addressable memory via the JTAG

debug interface.

Aliased addressing spaces are provided at the chip level so that specific bus interfaces can be selected explicitly where

needed. For example, the EC’s Bit Banding feature uses the System AHB-Lite bus to access resources normally

accessed via the DCode or ICode interface.

Note:

The EC executes most instructions in one clock cycle. If an instruction accesses code and data that are in

different RAM blocks, then it takes one clock cycle to access both code and data (done in

parallel). However, if the code and data blocks are in the same RAM block, then it takes two clock cycles

(one clock for code access and one clock for data access) since it must do it sequentially.

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