DS20006554A datasheet(87/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

Table 22 - Electrical Characteristics: I

2C Slave Interface Timing

VDDIO = 3.3V±5% or 2.5V±5% or 1.8V±5%

Characteristics

Symbol

Min.

Typ.

Max.

Units

Notes

SCL clock frequency

fSCL

400

kHz

Note 1

Hold time, START condition

tHD:STA

0.6

µs

Low time, SCL

tLOW

1.3

µs

High time, SCL

tHIGH

0.6

µs

Setup time, START condition

tSU:STA

0.6

µs

Data hold time

tHD:DAT

0.9

µs

Notes 2 and 3

Data setup time

tSU:DAT

100

Rise time

Note 4

Fall time

20 +

0.1Cb

300

Cb is cap. of

one bus line

Setup time, STOP condition

tSU:STO

0.6

µs

Bus free time between STOP/START

tBUF

1.3

µs

Pulse width of spikes which must be

suppressed by the input filter

tSP

Note 1:

The timing parameters in this table are specifically for 400kbps Fast Mode. Fast Mode devices are downward-compatible with

100kbps Standard Mode I2C bus timing. All parameters in this table are guaranteed by design or characterization. All values

referred to VIHmin and VILmax levels (see Table 7).

Note 2:

The device internally provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge

the undefined region of the falling edge of SCL. Other devices must provide this hold time as well per the I2C specification.

Note 3:

The I2C specification indicates that the maximum tHD:DAT spec only has to be met if the device does not stretch the low period

(tLOW) of the SCL signal. The device does not stretch the low period of the SCL signal.

Note 4:

Determined by choice of pull-up resistor.

Figure 20 - I

2C Slave Interface Timing

SDA

SCL

tHD:STA

tLOW

tHD:DAT

tHIGH

tSU:STA

tHD:STA

tSU:DAT

tSP

tSU:STO

tBUF

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