EMC2302 datasheet(41/70 Pages) MICROCHIP

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 2021 Microchip Technology Inc.

DS20006532A-page 41

EMC2301/2/3/5

6.17

Fan Spin Up Configuration

Registers

The Fan Spin Up Configuration registers control the

settings of the Spin Up Routine. These registers are

software locked (see Section 4.8 “Spin Up Routine”).

FAN SPIN - SPIN-UP CONFIGURATION REGISTER

(ADDRESSES 36H, 46H, 56H, 66H, 76H)

RW-0

DFCx[1:0]

NKCKx

SPLVx[2:0]

SPTx[1:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

DFCx[1:0]: Drive Fail Count, where “x” is 1 to 5, depending on device features. Determines when an

aging fan has been detected.

11 = 64 update periods

10 = 32 update periods

01 = 16 update periods

00 = Disabled

bit 5

NKCKx: No Kick, where “x” is 1 to 5, depending on device features. Kick refers to the 100% drive for

1/4 of the spin-up time.

1 = Spin-Up will not drive to 100% PWM

0 = Spin-Up will drive to 100% PWM

bit 4-2

SPLVx[2:0]: Spin-Up Level, where “x” is 1 to 5, depending on device features. This is the level the

spin-up routine will use.

111 = 65%

110 = 60%

101 = 55%

100 = 50%

011 = 45%

010 = 40%

001 = 35%

000 = 30%

bit 1-0

SPTx[1:0]: Spin-Up Time, where “x” is 1 to 5, depending on device features. This determines how long

the spin-up routine will run before releasing the drive.

11 = 2s

10 = 1s

01 = 500 ms

00 = 250 ms

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