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DSPIC33EP128GS708 bảng dữ liệu(PDF) 51 Page - Microchip Technology |
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DSPIC33EP128GS708 bảng dữ liệu(HTML) 51 Page - Microchip Technology |
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51 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 51 dsPIC33EPXXXGS70X/80X FAMILY 4.5.1 PAGED MEMORY SCHEME The dsPIC33EPXXXGS70X/80X family architecture extends the available Data Space through a paging scheme, which allows the available Data Space to be accessed using MOV instructions in a linear fashion for pre- and post-modified Effective Addresses (EAs). The upper half of the base Data Space address is used in conjunction with the Data Space Read Page (DSRPAG) register to form the Program Space Visibility (PSV) address. The Data Space Read Page (DSRPAG) register is located in the SFR space. Construction of the PSV address is shown in Figure 4-7. When DSRPAG<9> = 1 and the base address bit, EA<15> = 1, the DSRPAG<8:0> bits are concatenated onto EA<14:0> to form the 24-bit PSV read address. The paged memory scheme provides access to multiple 32-Kbyte windows in the PSV memory. The Data Space Read Page (DSRPAG) register, in combi- nation with the upper half of the Data Space address, can provide up to 8 Mbytes of PSV address space. The paged data memory space is shown in Figure 4-8. The Program Space (PS) can be accessed with a DSRPAG of 0x200 or greater. Only reads from PS are supported using the DSRPAG register. FIGURE 4-7: PROGRAM SPACE VISIBILITY (PSV) READ ADDRESS GENERATION 1 DSRPAG<8:0> 9 Bits EA 15 Bits Select Byte 24-Bit PSV EA Select EA (DSRPAG = don’t care) No EDS Access Select 16-Bit DS EA Byte EA<15> = 0 DSRPAG 1 EA<15> Note: DS read access when DSRPAG = 0x000 will force an address error trap. = 1 DSRPAG<9> Generate PSV Address 0 |
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