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DSPIC33EP128GS708 bảng dữ liệu(PDF) 20 Page - Microchip Technology

tên linh kiện DSPIC33EP128GS708
Giải thích chi tiết về linh kiện  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
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dsPIC33EPXXXGS70X/80X FAMILY
DS70005258C-page 20
 2016-2018 Microchip Technology Inc.
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 3 MHz < FIN < 5.5 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start up in the FRC mode first. The
default PLL settings, after a POR with an oscillator
frequency outside this range, will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLFBD, to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins, and drive the output to logic low.
2.9
Targeted Applications
• Power Factor Correction (PFC)
- Interleaved PFC
- Critical Conduction PFC
- Bridgeless PFC
• DC/DC Converters
- Buck, Boost, Forward, Flyback, Push-Pull
- Half/Full-Bridge
- Phase-Shift Full-Bridge
- Resonant Converters
• DC/AC
- Half/Full-Bridge Inverter
- Resonant Inverter
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-6.
FIGURE 2-4:
INTERLEAVED PFC
VAC
VOUT+
PGA/ADC Channel
PWM
ADC
PWM
|VAC|
k4
k3
FET
dsPIC33EPXXXGS70X/80X
Driver
VOUT-
ADC Channel
PGA/ADC
Channel
Channel
PGA/ADC
Channel
k2
FET
Driver
k1



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