DSPIC33EP128GS708 datasheet(25/484 Pages) MICROCHIP

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 2016-2018 Microchip Technology Inc.

DS70005258C-page 25

dsPIC33EPXXXGS70X/80X FAMILY

3.5

Programmer’s Model

The programmer’s model for the dsPIC33EPXXXGS70X/

80X family is shown in Figure 3-2. All registers in the

programmer’s model are memory-mapped and can be

manipulated directly by instructions. Table 3-1 lists a

description of each register.

In addition to the registers contained in the programmer’s

model, the dsPIC33EPXXXGS70X/80X devices contain

control registers for Modulo Addressing, Bit-Reversed

Addressing and interrupts. These registers are

described in subsequent sections of this document.

All registers associated with the programmer’s model

are memory-mapped, as shown in Table 3-1.

TABLE 3-1:

PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

Description

W0 through W15(1)

Working Register Array

W0 through W14(1)

Alternate 1 Working Register Array

W0 through W14(1)

Alternate 2 Working Register Array

W0 through W14(1)

Alternate 3 Working Register Array

W0 through W14(1)

Alternate 4 Working Register Array

ACCA, ACCB

40-Bit DSP Accumulators

23-Bit Program Counter

ALU and DSP Engine STATUS Register

SPLIM

Stack Pointer Limit Value Register

TBLPAG

Table Memory Page Address Register

DSRPAG

Extended Data Space (EDS) Read Page Register

RCOUNT

REPEAT Loop Counter Register

DCOUNT

DO Loop Counter Register

DOSTARTH(2), DOSTARTL(2)

DO Loop Start Address Register (High and Low)

DOENDH, DOENDL

DO Loop End Address Register (High and Low)

CORCON

Contains DSP Engine, DO Loop Control and Trap Status bits

Note 1:

Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context.

The DOSTARTH and DOSTARTL registers are read-only.

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