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DSPIC33EP128GS708 bảng dữ liệu(PDF) 262 Page - Microchip Technology |
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DSPIC33EP128GS708 bảng dữ liệu(HTML) 262 Page - Microchip Technology |
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262 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 262 2016-2018 Microchip Technology Inc. bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1 0 transition) resets the receiver buffer and the UxRSR to the empty state bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/ PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation. |
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