68HC05JB4 datasheet(5/134 Pages) FREESCALE

5 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

MOTOROLA

REV 2

iii

TABLE OF CONTENTS

Section

Page

SECTION 8

MULTI-FUNCTION TIMER

8.1

OVERVIEW...................................................................................................... 8-2

8.2

COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2

8.3

MFT REGISTERS ............................................................................................ 8-3

8.3.1

Timer Counter Register (TCNT) $09 ........................................................... 8-3

8.3.2

Timer Control/Status Register (TCSR) $08 ................................................. 8-3

8.4

OPERATION DURING STOP MODE .............................................................. 8-4

8.5

COP CONSIDERATION DURING STOP MODE............................................. 8-4

SECTION 9

16-BIT TIMER

9.1

TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2

9.2

ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4

9.3

INPUT CAPTURE REGISTERS ...................................................................... 9-5

9.4

OUTPUT COMPARE REGISTERS ................................................................. 9-6

9.5

TIMER CONTROL REGISTER (TCR) ............................................................. 9-8

9.6

TIMER STATUS REGISTER (TSR)................................................................. 9-9

9.7

TIMER OPERATION DURING WAIT MODE................................................. 9-10

9.8

TIMER OPERATION DURING STOP MODE ................................................ 9-10

SECTION 10

UNIVERSAL SERIAL BUS MODULE

10.1

FEATURES .................................................................................................... 10-1

10.2

OVERVIEW.................................................................................................... 10-2

10.2.1

USB Protocol ............................................................................................. 10-2

10.2.2

Reset Signaling.......................................................................................... 10-8

10.2.3

Suspend..................................................................................................... 10-9

10.2.4

Resume After Suspend.............................................................................. 10-9

10.2.5

Low Speed Device................................................................................... 10-10

10.3

CLOCK REQUIREMENTS........................................................................... 10-10

10.4

HARDWARE DESCRIPTION....................................................................... 10-10

10.4.1

Voltage Regulator .................................................................................... 10-11

10.4.2

USB Transceiver...................................................................................... 10-11

10.4.3

Receiver Characteristics.......................................................................... 10-12

10.4.4

USB Control Logic ................................................................................... 10-14

10.5

I/O REGISTER DESCRIPTION ................................................................... 10-17

10.5.1

USB Address Register (UADDR)............................................................. 10-18

10.5.2

USB Interrupt Register 0 (UIR0) .............................................................. 10-19

10.5.3

USB Interrupt Register 1 (UIR1) .............................................................. 10-20

10.5.4

USB Control Register 0 (UCR0) .............................................................. 10-21

10.5.5

USB Control Register 1 (UCR1) .............................................................. 10-22

10.5.6

USB Control Register 2 (UCR2) .............................................................. 10-23

Freescale Semiconductor, Inc.

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