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CDCDB800 bảng dữ liệu(PDF) 1 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  CDCDB800 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5
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CDCDB800 bảng dữ liệu(HTML) 1 Page - Texas Instruments

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CDCDB800 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5
1 Features
• 8 LP-HCSL outputs with programmable integrated
85-Ω (default) or 100-Ω differential output
terminations
• 8 hardware output enable (OE#) controls
• Additive phase jitter after PCIE Gen5 filter: < 25 fs,
RMS (maximum)
• Additive phase jitter after DB2000Q filter: < 38 fs,
RMS (maximum)
• Supports PCIe Gen 4 and Gen 5 Common Clock
(CC) and Individual Reference (IR) architectures
– Spread spectrum-compatible
• Output-to-output skew: < 50 ps
• Input-to-output delay: < 3 ns
• Fail-safe input
• Programmable output slew rate control
• 3.3-V core and IO supply voltages
• Hardware-controlled low power mode (PD#)
• Current consumption: 72 mA maximum
• 6-mm × 6-mm, 48-pin VQFN package
2 Applications
• Microserver & tower server
• Storage area network & host bus adapter card
• Network attached storage
• Hardware accelerator
• Rack server
3 Description
The CDCDB800 is a 8-output LP-HCSL, DB800ZL-
compliant, clock buffer capable of distributing the
reference clock for PCIe Gen 1-5, QuickPath
Interconnect (QPI), UPI, SAS, and SATA interfaces.
The SMBus interface and eight output enable pins
allow the configuration and control of all eight
outputs individually. The CDCDB800 is a DB800ZL
derivative buffer and meets or exceeds the system
parameters in the DB800ZL specification. It also
meets or exceeds the parameters in the DB2000Q
specification. The CDCDB800 is packaged in a 6-mm
× 6-mm, 48-pin VQFN package.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
CDCDB800
VQFN (48)
6.00 mm × 6.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
PCIe Gen 4-5
Clock
Generator
CDCDB800
8x LP-HSCL Output Buffer
SMBus
Control
OE#
Control
LP-HCSL
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
LP-HCSL
8
PCIe PHY
PCIe PHY
PCIe Device
Control Interface
CDCDB800 System Diagram
CDCDB800
SNAS818 – JULY 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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