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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CDCDB800 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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CDCDB800 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 31 page  VDD, VDD_R = 3.3 V ± 5 %, −40 °C ≤ TA ≤ 105 °C. Typical values are at VDD = VDD_R = 3.3 V, 25 °C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEDGE Differential edge rate Measured (+-150 mV) around VCROSS (7) 2 4 V/ns DtEDGE Edge rate matching Measured (+-75 mV) VCROSS (7) 20 % tSTABLE Power good assertion to stable clock output CKPWRGD_PD# pin transistions from 0 to 1, fIN = 100 MHz Measured when positive output reaches 0.2V 1.8 ms tDRIVE_PD# Power good assertion to outputs driven high CKPWRGD_PD# pin transistions from 0 to 1, fIN = 100 MHz Measured when positive output reaches 0.2V 300 µs tOE Output enable assertion to stable clock output OEx# pin transistions from 1 to 0 10 CLKIN Periods tOD Output enable de-assertion to no clock output OEx# pin transistions from 0 to 1 10 tPD Power down assertion to no clock output CKPWRGD_PD# pin transistions from 1 to 0 3 tDCD Duty cycle distortion Differential; fIN = 100MHz, fIN_DC = 50% –1 1 % tDLY Propagation delay (5) 0.5 3 ns tSKEW Skew between outputs (6) 50 ps tDELAY(IN- OUT) Input to output delay variation Input-to-output delay variation at 100 MHz across voltage and temperature –250 250 ps JCKx_DB2000 Q (7) Additive jitter for DB2000Q DB2000Q filter, for input of 200 mV differential swing @ 1.5 V/ns 0.038 ps, RMS JCKx_PCIE (7) Additive jitter for PCIe6.0 PLL BW: 0.5 - 1 MHz; CDR = 10 MHz Input clock slew rate = 2 V/ns 0.02 ps, RMS Additive jitter for PCIe5.0 PCIe5.0 filter 0.025 Additive jitter for PCIe4.0 PLL BW = 2 - 5 MHz; CDR = 10 MHz Input clock slew rate ≥ 1.8 V/ns 0.06 Additive jitter for PCIe3.0 Input clock slew rate ≥ 0.6 V/ns 0.1 JCKx Additive jitter fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to 20 MHz integration bandwidth. 100 160 fs, RMS NF Noise floor fIN = 100 MHz; fOffset ≥ 10 MHz Input clock slew rate ≥ 3 V/ns –160 -155 dBc/Hz SMBUS INTERFACE, OEx#, CKPWRGD_PD# VIH High level input voltage 2.0 V VIL Low level input voltage 0.8 IIH Input leakage current With internal pull-up/pull-down GND ≤ VIN ≤ VDD –30 30 µA IIL Input leakage current With internal pull-up/pull-down GND ≤ VIN ≤ VDD –30 30 µA IIH Input leakage current Without internal pull-up/pull- down GND ≤ VIN ≤ VDD −5 5 µA IIL Input leakage current Without internal pull-up/pull- down GND ≤ VIN ≤ VDD −5 5 µA CDCDB800 SNAS818 – JULY 2021 www.ti.com 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CDCDB800 |
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