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tên linh kiện CDCDB800
Giải thích chi tiết về linh kiện  CDCDB800 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5
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CDCDB800 bảng dữ liệu(HTML) 4 Page - Texas Instruments

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Table 5-1. Pin Functions (continued)
PIN
I/O TYPE(2)
DESCRIPTION
NAME
NO.
MANAGEMENT AND CONTROL (1)
CKPWRGD_PD#
1
I, S, PD
Clock Power Good and Power Down multi-function input pin with internal 180-kΩ
pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can
be left no connect. After PWRGD has been asserted high for the first time, the pin
becomes a PD# pin and it controls power-down mode:
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
OE0#
11
I, S, PD
Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 0.
HIGH: disable output channel 0.
OE1#
18
I, S, PD
Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 1.
HIGH: disable output channel 1.
OE2#
23
I, S, PD
Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 2.
HIGH: disable output channel 2.
OE3#
24
I, S, PD
Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 3.
HIGH: disable output channel 3.
OE4#
30
I, S, PD
Output Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 4.
HIGH: disable output channel 4.
OE5#
31
I, S, PD
Output Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 5.
HIGH: disable output channel 5.
OE6#
37
I, S, PD
Output Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 6.
HIGH: disable output channel 6.
OE7#
41
I, S, PD
Output Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically
connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 7.
HIGH: disable output channel 7.
SMBUS AND SMBUS ADDRESS
SMBDAT
6
I / O
Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup
resistor. The recommended pullup resistor value is > 8.5k.
SMBCLK
7
I
Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external
pullup resistor. The recommended pullup resistor value is > 8.5k.
SMBWRTLOCK
46
I, PD
SMBWRTLOCK: Disables write commands on SMBus. All writes will be ignored
when SMBWRTLOCK is asserted (reads are not affected). Internal 180-kΩ
pulldown, active low.
0 = SMBus write enabled.
1 = SMBus write disabled.
SUPPLY VOLTAGE AND GROUND
GNDR
2
G
Ground.
VDDR
3
P
Power supply input for input clock receiver. Connect to 3.3-V power supply rail with
decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin
between power supply and ground.
VDD
10, 15, 19, 27, 34,
38, 42, 44
P
3.3-V power supply for output channels and core voltage.
CDCDB800
SNAS818 – JULY 2021
www.ti.com
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