ACE25AA320GFMLTH datasheet(35/67 Pages) ACE

tên linh kiện	ACE25AA320GFMLTH

Giải thích chi tiết về linh kiện	Serial NOR Flash Memory 3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

PDF	67 Pages

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

The Chip Erase command sequence: CS# goes low→sending Chip Erase command→CS# goes high.

The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the

command code has been latch in, otherwise the Chip Erase command is not executed. As soon as CS# is

driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase

cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The

Chip Erase (CE) command is executed if the Block protected by (BP2, BP1, BP0) bits. The Chip

Erase(CE) command is ignored if one or more sectors are protected.

Figure19. Chip Erase Sequence Diagram

Figure19a. Chip Erase Sequence Diagram (QPI)

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