ACE25AA320GFMLTH datasheet(34/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

The 64KB Block Erase command sequence: CS# goes low→sending 64KB Block Erase command→

3-byte address on SI→CS# goes high. The command sequence is shown in Figure18. CS# must be

driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block

Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle

(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be

read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the

self-timed Block Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset t. A

64KB Block Erase (BE) commands applied to a block which is protected by the Block Protect (BP4,

BP3,BP2, BP1, BP0) bits (see Table1 & 1.1) will not be executed.

Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE)

command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS#

must be driven Low for the entire duration of the sequence.

Figure18. 64KB Block Erase Sequence Diagram

Figure18a. 64KB Block Erase Sequence Diagram (QPI)

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