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ACE25AA320GFMLTH bảng dữ liệu(PDF) 18 Page - ACE Technology Co., LTD. |
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ACE25AA320GFMLTH bảng dữ liệu(HTML) 18 Page - ACE Technology Co., LTD. |
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18 / 67 page ![]() ACE25AA320G Serial NOR Flash Memory 3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase VER 1.2 18 Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low→sending Write Disable command→CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Read Status Register (RDSR) (05H or 35H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8. Figure3. Write Disable Sequence Diagram Figure3a. Write Disable Sequence Diagram (QPI) |
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