MCP3565RT-ESLASHSFX datasheet(75/108 Pages) MICROCHIP

75 / 108 page



2020-2021 Microchip Technology Inc.

DS20006401C-page 75

MCP3565R

6.6

Locking/Unlocking Register Map

Write Access

The MCP3565R digital interface includes an advanced

security feature that allows locking or unlocking the

miscommunication that can corrupt the desired config-

uration of the device, especially an SPI read becoming

an SPI write because of the noisy environment.

The last register address of the incremental write loop

(0xD: LOCK) contains the LOCK[7:0] bits. If these bits

are equal to the password value (0xA5), the register

map write access is not locked. Any write can take

place and the communications are not protected. The

MCP3565R device is, by default after POR, in an

unlocked state (LOCK[7:0] = 0xA5).

When the LOCK[7:0] bits are not equal to 0xA5, the

and the full device configuration is write- protected. Any

write to an address other than 0xD will yield no result.

All the register addresses, except the address 0xD,

become read-only. In this case, if the user wants to

change the configuration, the LOCK[7:0] bits have to

be reprogrammed back to 0xA5 before sending the

desired Write command.

The LOCK[7:0] bits are located in the last register of the

Incremental Write address loop, so the user can

program the entire register map, starting from 0x1 to

0xD, within one continuous write sequence and then

lock the configuration at the end of the sequence by

writing all zeros (for example) in the 0xD address.

6.7

Detecting a Configuration Change

through CRC-16 Checksum on the

Interrupt Flag

In order to prevent internal corruption and to provide

additional security on the register map configuration, the

MCP3565R device includes an automatic and continu-

ous CRC checksum calculation on the full register map

Configuration bits. This calculation is not the same as

the communication CRC checksum described in

Section 6.5 “Securing Read Communications

through CRC-16 Checksum”.

This calculation takes the contents of the register map,

from addresses 0x1 to 0xF, and produces a checksum

which is held in the CRCCFG[15:0] bits located in the

CRCCFG register (address: 0xF). The CRC checksum

for the register map uses the 16-bit CRC-16 ANSI

polynomial as defined in the IEEE 802.3 Standard:

x16 + x15 + x2 + 1.

Since this feature is intended to protect the configuration

of the device, this calculation is run continuously only

when the register map is locked (LOCK[7:0]), which is

different than 0xA5 (see

Section 6.6 “Locking/Unlock-

ing Register Map Write Access”). If the register map is

unlocked (for example, after POR), the CRCCFG[15:0]

bits are cleared and no CRC is calculated.

The

DR_STATUS,

CRCCFG_STATUS

and

POR_STATUS bits are set to ‘1’ (default) and the

CRCCFG[15:0] bits are set to ‘0’ (default) for this calcu-

lation, as they could vary and lead to unwanted CRC

errors.

After the DR_STATUS, CRCCFG_STATUS and

POR_STATUS bits are cleared (with a read on the IRQ

be verified by reading all registers in an incremental

read sequence and by using the CRC communication.

At the second incremental read loop, the checksum

provided by the CRC communication must be equal to

all zeros if the checksum on the register map is correct.

The checksum will be calculated for the first time in

11 DMCLK periods. This first value will then be the

reference checksum value and will be latched internally

until an unlocking of the register map occurs. The

checksum will then be calculated continuously every

11 DMCLK periods and checked against the reference

checksum.

If the checksum is different than the reference, an

interrupt flag is generated on the CRCCFG_STATUS

bit within the STATUS byte on SDO, and on the

CRCCFG_STATUS bit in the IRQ register. The inter-

rupt flag is maintained on both mechanisms until the

write access is unlocked, the interrupt on both interrupt

mechanisms is cleared when the interrupt is read (read

STATUS byte or read IRQ register).

At power-up, the interrupt is not present and the

writing its configuration, the user needs to lock the

bits) to be able to use the interrupt flag and to calculate

the checksum of the register map.

MCP3565RT-E/SFX bảng dữ liệu(PDF) 75 Page - Microchip Technology

MCP3565RT-E/SFX bảng dữ liệu(HTML) 75 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL