MCP3565RT-ESLASHSFX datasheet(48/108 Pages) MICROCHIP

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MCP3565R

DS20006401C-page 48

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2020-2021 Microchip Technology Inc.

When VREF_SEL = 0, the reference voltage is set to

External mode. The REFIN+/OUT pin becomes an

input. In this case, the REFIN+/OUT pad is directly tied

to the VREF+ input of the ADC. There is no input buffer

in the differential input voltage reference path in this

mode, so the external voltage reference should include

a buffer to be able to charge the internal voltage

reference sampling capacitors.

When VREF_SEL = 1, the REFIN+/OUT is internally

buffered to produce a 2.4V buffered reference voltage

at the VREF+ input of the ADC. Section 5.7.2 “Internal

Voltage Reference Buffer” details the architecture of

the voltage reference buffer.

In this mode, the REFIN+/OUT pin becomes an output

and the reference voltage is generated internally.

The structure of the internal voltage reference is based

on a band gap voltage reference source, giving a 1.2V

output directly connected to a low noise chopper buffer,

configured with a gain of 2x, to give a 2.4V output on

the REFIN+/OUT pad. The internal reference has a

very low typical temperature coefficient of 15 ppm/°C

for extended temperature range and 9 ppm/°C for

industrial temperature range, allowing the ADC output

codes to have the least variation corresponding to the

temperature ranges, since they are proportional to

(1/VREF).

5.7.2

INTERNAL VOLTAGE REFERENCE

BUFFER

When VREF_SEL = 1, the voltage reference buffer is

enabled. It is only powered on when the ADC state is in

Reset or in Conversion mode and is powered off in

Shutdown mode.

The buffer is designed to be able to drive the ADC

reference input that is sampling the reference voltage.

The REFIN- pin is not buffered and is connected

directly to the ADC inverting voltage reference input

(VREF-).

The offset induced by the buffer may slightly vary

between the two possible gain selections, as well as its

temperature dependency and bandwidth; therefore, it

has to be characterized separately. The buffer injects a

certain quantity of 1/f noise into the system that can be

modulated with the incoming input signals and can limit

the SNR performance at higher OSR values

(OSR > 256).

To overcome this limitation, the buffer includes an

auto-zeroing algorithm that greatly reduces (cancels

out) the 1/f noise and cancels the offset value of the

reference buffer. As a result, the SNR of the system is

not affected by this 1/f noise component of the

reference buffer, even at maximum OSR values. This

auto-zeroing algorithm is performed synchronously

with the DMCLK and can be enabled or disabled with

the AZ_VREF bit setting in the CONFIG2 register.

When AZ_VREF = 1 (default), the auto-zeroing is

enabled, which cancels out the 1/f noise and improves

the SNR, while not impacting the THD performance.

This mode is recommended for higher OSR values

(OSR > 256).

When AZ_VREF = 0, the reference auto-zeroing

algorithm is disabled. This setting should be reserved

for lower OSR values, where higher ADC speed is

more important than accuracy.

If the application is susceptible to high-frequency noise,

using AZ_VREF = 0 or a proper low-pass filter at the

VREF output pin (to filter out the chopper frequency

components from the buffered output) is recommended.

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