MCP3565RT-ESLASHSFX datasheet(53/108 Pages) MICROCHIP

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2020-2021 Microchip Technology Inc.

DS20006401C-page 53

MCP3565R

FIGURE 5-11:

ADC Start-up Timer Timing Diagram.

5.12 Master Clock Selection/Internal

Oscillator

The device includes three possible clock modes for the

master clock generation. The Master Clock (MCLK) is

used by the ADC to perform conversions and is also used

by the digital portion to generate the different digital

timers. The clock mode selection is made through the

CLK_SEL[1:0] bits located in the CONFIG0 register. The

possible selections are described in Table 5-13.

The master clock is not propagated in the chip when the

chip enters the Full Shutdown mode (see

Section 5.10

“Low-Power Shutdown Modes”). MCP3565R is a low

pin count device, targeted to applications requiring a

smaller PCB footprint, so there is no dedicated pin for the

MCLK input/output on this device. The SCK pin is used

for this function, on top of being used as the clock input

for the digital interface. SCK is always the clock input for

the digital interface at all times. Any change to the

CLK_SEL bits is following a specific sequence described

Section 6.9 “Master Clock Input/Output Modes”.

Each reset and restart resets all internal phases to their

default values and can lead to a possible temporary duty

cycle change at the clock output pin.

TABLE 5-13: CLOCK SELECTION BITS

5.12.1

EXTERNAL MASTER CLOCK MODE

(CLK_SEL[1:0] = 0x)

The External Clock mode is used to input the MCLK

clock necessary for the ADC conversions and can

accept duty cycles with a large range, since the clock is

redivided internally to generate the different internal

phases.

The external clock can be provided on the SCK pin.

Therefore, the SCK pin in this mode has a dual func-

tionality, as it is also the clock input pin for the digital

interface. In this mode, SCK = MCLK at all times and

the digital interface is synchronous with the master

clock. When running conversions, SCK has to be

continuously clocking at a constant frequency as it is

defined for the MCLK input to ensure proper ADC

accuracy. In this case, communications using the SPI

interface should be synchronized on this free-running

clock and can be framed with a proper usage of CS pin.

5.12.2

INTERNAL OSCILLATOR

The device includes an internal RC-type oscillator

frequency of this internal oscillator ranges from

3.3 MHz to 6.6 MHz. The oscillator is not trimmed in

production; therefore, the precision of the center

frequency is approximately ±30% from chip to chip.

The duty cycle of the internal oscillator is centered

around 50% and varies very slightly from chip to chip.

The internal oscillator has no reset feature and keeps

running once selected.

ADC Start-up

Timer Decimal

Code

ADC_MODE

DMCLK

256

Continuous Clocking

Switching Between ADC_MODE = 10 and 11

has no Effect on the Timer

Timer Reset

ADC Ready to Convert

SPI

Wri te

ADC_M ODE = 1x

Wri te

ADC _M ODE = 0x

Write

AD C_M ODE = 1x

Wri te

ADC_M ODE = 1x

Timer Reset

Timer

Countdown

CLK_SEL[1:0]

Clock Mode

SCK Pin

00 or 01

External clock

MCLK digital input

Internal RC

Oscillator,

no clock output

High-Z MCLK and SCK

are asynchronous

Internal RC

Oscillator with clock

output

AMCLK is present as

an output on the SCK

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