K32L2AX datasheet(18/96 Pages) NXP

18 / 96 page

Table 6. LLWU Wakeup Sources

(continued)

IRQ

Module source or pin name

LLWU_M0DR

LPTMR0 asynchronous DMA

LLWU_M3DR

LPTMR1 asynchronous DMA

LLWU_M4DR

TSI asynchronous DMA

LLWU_M6DR

LPTMR0 trigger

LLWU_M7DR

LPTMR1 trigger

2.1.10 Debug controller

The debug system of this device is based on the Arm CoreSight™ architecture, and is

configured to provide the maximum flexibility as allowed by the restrictions of the

pinout and other available resources.

The MCU has a single M0+ CPU available for customer application use.

Debug provides register and memory accessibility from the external debugger interface,

basic run/halt control, plus 2 breakpoints and 2 watchpoints. Additionally, it supports

Arm's Micro Trace Buffer (MTB) capability to provide simple program trace. Only one

debug interface is supported: Serial Wire Debug (SWD). The SWD interface provides

the capability for debugger tools to interface to the CPU.

2.2 Peripheral features

2.2.1 16-bit SAR ADC

This device contains one 16-bit successive approximation ADC. The ADC supports

both software and hardware triggers.

The number of ADC channels present on the device is determined by the pinout of the

specific device package.

2.2.2 Crossbar Switch Lite (AXBS-Lite)

The information found here provides information on the layout, configuration, and

programming of the crossbar switch.

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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