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MCP47FVB01 bảng dữ liệu(PDF) 58 Page - Microchip Technology

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MCP47FVB01 bảng dữ liệu(HTML) 58 Page - Microchip Technology

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MCP47FVBXX
DS20005405A-page 58
 2015 Microchip Technology Inc.
FIGURE 7-7:
Continuous Read Command Of Specified Address.
Control Byte
Read Command
S0
AD
AD AD AD AD
A1 1 X A Sr
1
2
3
4
I2C™ Slave Address
Memory Address Command
Control Byte
Read bits
D
DD D D
D D D
A
D
DD DD
DD D
A
1A
Read Data bits
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
0
SA
6
SA
5
SA
4
SA
3
SA
2
SA
1
SA
0
SA
6
SA
5
SA
4
SA
3
SA
2
SA
1
SA
0
I2C Slave Address
Read bits
D
DDD D
D D D
A
D
DDDD
DD D
A
Read Data bits
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
Read bits
D
DDD D
D D D
A
D
DDD D
D D D
A
Read Data bits
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
P
Write bit
Repeated Start bit
Start bit
ACK bit (1)
ACK bit (1)
Read bit
ACK bit (4)
ACK bit (5)
Stop bit (2, 3)
ACK bit (1)
ACK bit (5)
ACK bit (4)
ACK bit (4)
ACK bit (5)
Note 1:
The Acknowledge bit is generated by the MCP47FVBXX.
2:
At the falling edge of the SCL pin for the Read command ACK bit, the MCP47FVBXX device updates
the value of the specified device register.
3:
This command sequence does not need to terminate (using the Stop bit), and the Read command can
be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”).
4:
Master Device is responsible for A / A signal. If a A signal occurs, the MCP47FVBXX will abort this
transfer and release the bus.
5:
The Master Device will Not Acknowledge, and the MCP47FVBXX will release the bus so the Master
Device can generate a Stop or Repeated Start condition.



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