MCP47FVB01 datasheet(23/92 Pages) MICROCHIP

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DS20005405A-page 23

MCP47FVBXX

Timing Table Notes:

Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).

Not Tested. This parameter ensured by characterization.

The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge

(Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not.

Use Cb in pF for the calculations.

A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not

unintentionally create a Start or Stop condition.

A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the

requirement tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch

the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output

the next data bit to the SDA line

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL

line is released.

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (mini-

mum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

Ensured by the TAA 3.4 MHz specification test.

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