NUC029-FAE datasheet(9/75 Pages) NUVOTON

9 / 75 page

NUC029xDE

Apr 09, 2020

Page 9 of 75

Rev 1.04

– Supports independent mode for PWM output/Capture input channel

– Supports complementary mode for 3 complementary paired PWM output channel

 Dead-time insertion with 12-bit resolution

 Two compared values during one period

– Supports 12-bit pre-scalar from 1 to 4096

– Supports 16-bit resolution PWM counter

 Up, down and up/down counter operation type

– Supports mask function and tri-state enable for each PWM pin

– Supports brake function

 Brake source from pin and system safety events (clock failed, Brown-out detection and

CPU lockup)

 Noise filter for brake source from pin

 Edge detect brake source to control brake state until brake interrupt cleared

 Level detect brake source to auto recover function after brake condition removed

– Supports interrupt on the following events:

 PWM counter match zero, period value or compared value

 Brake condition happened

– Supports trigger ADC on the following events:

 PWM counter match zero, period value or compared value

– Supports up to 12 capture input channels with 16-bit resolution

– Supports rising edges, falling edges or both edges capture condition

– Supports input rising edges, falling edges or both edges capture interrupt

– Supports rising edges, falling edges or both edges capture with counter reload option

 UART

– Up to four UART controllers

– UART0 and UART1 ports with flow control (TXD, RXD, nCTS and nRTS)

– UART0, UART1 and UART2 with 16-byte FIFO for standard device

– Supports IrDA (SIR) and LIN function

– Supports RS-485 9-bit mode and direction control

– Supports auto baud-rate generator

 SPI

– One set of SPI controller

– Supports SPI Master/Slave mode

– Full duplex synchronous serial data transfer

– Variable length of transfer data from 8 to 32 bits

– MSB or LSB first data transfer

– Rx and Tx on both rising or falling edge of serial clock independently

– Supports Byte Suspend mode in 32-bit transmission

– Supports three wire, no slave select signal, bi-direction interface

 I

– Up to two sets of I

2C devices

– Master/Slave mode

– Bidirectional data transfer between masters and slaves

– Multi-master bus (no central master)

– Arbitration between simultaneously transmitting masters without corruption of serial data on

the bus

– Serial clock synchronization allowing devices with different bit rates to communicate via one

serial bus

– Serial clock synchronization used as a handshake mechanism to suspend and resume serial

transfer

– Programmable clocks allowing for versatile rate control

– Supports multiple address recognition (four slave address with mask option)

– Supports wake-up function

 ADC

– 12-bit SAR ADC with 1000 kSPS

– Up to 8-ch single-end input or 4-ch differential input

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