ATMEGA640 datasheet(128/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Table 16-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,

but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 122 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the

counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see

Table 16-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on

Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation”

on page 144).

Note:

1. MAX

= 0xFF

2. BOTTOM = 0x00

Table 16-7.

Compare Output Mode, Phase Correct PWM Mode(1)

COM0B1

COM0B0

Description

Normal port operation, OC0B disconnected

Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when

down-counting

Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when

down-counting

Table 16-8.

Waveform Generation Mode Bit Description

Mode

WGM2

WGM1

WGM0

Timer/Counter Mode of

Operation

TOP

Update of

OCRx at

TOV Flag

Set on(1)(2)

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCRA

Immediate

MAX

Fast PWM

0xFF

TOP

MAX

Reserved

–

PWM, Phase Correct

OCRA

TOP

BOTTOM

Reserved

–

Fast PWM

OCRA

BOTTOM

TOP

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