ATMEGA640 datasheet(351/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 30-17. Flash Data Byte Register

The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which

eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automati-

cally feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its

operation transparently for the user. However, if too few bits are shifted between each Update-DR state during

page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are

at least 11 TCK cycles between each Update-DR state.

30.9.12

Programming Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 30-18 on page 347.

30.9.13

Entering Programming Mode

1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Programming Enable Register.

30.9.14

Leaving Programming Mode

1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the programming Enable

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

30.9.15

Performing Chip Erase

1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming instruction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 30-14 on

page 338).

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

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