ATMEGA640 datasheet(239/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 24-5. Data Packet Format

24.3.5

Combining Address and Data Packets into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP con-

dition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-

ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can

extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too

fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extend-

ing the SCL low period will not affect the SCL high period, which is determined by the Master. As a consequence,

the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle.

Figure 24-6 shows a typical data transmission. Note that several data bytes can be transmitted between the

SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software.

Figure 24-6. Typical Data Transmission

24.4 Multi-master Bus Systems, Arbitration, and Synchronization

The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure

that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time.

Two problems arise in multi-master systems:

•

An algorithm must be implemented allowing only one of the masters to complete the transmission. All other

masters should cease transmission when they discover that they have lost the selection process. This

selection process is called arbitration. When a contending master discovers that it has lost the arbitration

process, it should immediately switch to Slave mode to check whether it is being addressed by the winning

master. The fact that multiple masters have started transmission at the same time should not be detectable to

the slaves, that is, the data being transferred on the bus must not be corrupted.

•

Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial

clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the

arbitration process.

Data MSB

Data LSB

ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

SLA+R/W

Data Byte

STOP, REPEATED

START or Next

Data Byte

Data MSB

Data LSB

ACK

SDA

SCL

START

789

Addr MSB

Addr LSB

R/W

ACK

SLA+R/W

STOP

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