ATMEGA640 datasheet(176/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

20.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to

the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the

timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings

define whether the OC2x pin is set, cleared or toggled).

20.5.2

Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock

cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2

without triggering an interrupt when the Timer/Counter clock is enabled.

20.5.3

Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are

risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the

Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be

missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM

when the counter is downcounting.

The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output.

The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal

mode. The OC2x Register keeps its value even when changing between Waveform Generation modes.

Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the

COM2x1:0 bits will take effect immediately.

20.6 Compare Match Output Unit

The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0

bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the

OC2x pin output source. Figure 20-7 on page 177 shows a simplified schematic of the logic affected by the

COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When

referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.

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