VSC8221 datasheet(101/138 Pages) MICROSEMI

101 / 138 page

VSC8221

Data Sheet

VMDS-10106 Revision 4.1

December 2006

101 of 106

106

20E.7:6 - Media Mode Status

Bits 20E.7:6 reflect the media interface status.

20E.5 - SerDes Line impedance

The internal termination impedance of the high speed serial interface inside the VSC8221 can be selected using bit 20E.5. This

applies to the SerDes/SGMii pins on the device. The reset value of this bit is determined by the SerDes Line impedance bit in

the CMODE hardware configuration.

20E.4 - Enable Link Speed Auto-Downshift

When bit 20E.4 is set to a “1”, the VSC8221 will “downshift” the auto-negotiation advertisement to 100BASE-TX after the

number of failed 1000BASE-T auto-negotiation attempts specified in bits 20E.3:2. The reset value of this bit is determined by

the Link Speed Downshift bit in the CMODE hardware configuration.

20E.3:2 - Link Speed Auto-Downshift Control

Bits 20E.3:2 determine the number of unsuccessful 1000BASE-T auto-negotiation attempts that are required before the auto-

negotiation advertisement is “downshifted” to 100BASE-TX. These bits are valid only if bit 20E.4 is set.

20E.1 - Link Speed Auto-Downshift Status

When bit 20E.1 is set to a “1” and bit 20E.4 is set to a “1”, the current link speed is the result of a “downshift” to 100BASE-TX.

When bit 20E.1 is set to a “1” and bit 20E.4 is cleared, the current link requires a “downshift” in order to be established.

20E.0 - Reserved

23.3.6 Register 21E (15h) - EEPROM interface Status and Control Register

Bit

Name

Access

States

Reset Value

Sticky

SFP MODE

R/W

1 = SFP MODE

0 = iEEE MODE

CMODE

Re-Read EEPROM on Software

Reset

R/W

1 = Contents of EEPROM should be re-

read on software reset

0 = Contents of EEPROM should not be

re-read on software reset

EEPROM Access Enable

R/W

1 = Execute read or write to EEPROM

EEPROM Read/Write

R/W

1 = Read from EEPROM

0 = Write to EEPROM

EEPROM Ready1

1 After an EEPROM write operation, the station manager or controller must wait an additional 10 ms before performing the next EEPROM read or write operation.

This delay is needed for the EEPROM to complete its internal memory write process. Note that this additional wait is not needed after an EEPROM read operation.

1 = EEPROM is ready for read/write

0 = EEPROM is busy

10:0

EEPROM Address

R/W

EEPROM address to read/write

000 00000000

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