VD6640 datasheet(61/126 Pages) STMICROELECTRONICS

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DocID023597 Rev 11

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VG6640, VD6640

Control interface

125

4.2.14

Output interface control registers [0x249B - 0x24A3]

Table 27. Output interface control registers [0x249B - 0x24A3]

Index

Byte

Data

type

Default

Type

Comment

0x249B

SlcTrailerControl

8UI

0x00

[1:0] - Stat source:

0 = Short expo pipe

1 = Medium expo pipe

2 = Longx1 expo pipe

3 = Longx4 expo pipe

0x249C

SmiaOutIF_Control

8UI

0x01

[2] - CSI2 DataClip enable:

0 = Data unclipped

1 = Data clipped to 16 min

[1] - CSI2 ULPS mode enable:

0 = ULPS disabled

1 = ULPS enable

[0] - UIx4AutoEnable:

0 = Manual UIx4 value control

1 = Automatic UIx4 value control

0x24A2

ParOutIF_Drive

8UI

0x02

[1:0] - PinDriveStrength:

1 = All signals low drive strength

except PIXCLK and GPIO.

2 = All signals normal drive strength

0x24A3

ParOutIF_Control

8UI

0x04

[7] - SyncCodeProtect:

0 = Raw data

1 = Data sync code protected

[6] - InvertPixelClock:

1 = Invert pixel clock

[5] - InterframeClockGating:

0 = Interframe clock gated

[4] - InterlineClockGating

0 = Interline clock gated

[3] - BlankLineClockGating

0 = Blank line clock gated

[2] - GatingControl:

0 = Gating control enabled

1 = Free running clock (default)

[1] - VSyncPolarity:

1 = VSync active low

[0] - HSyncPolarity

1 = HSync active low

NOTE - use of some clock gating

combinations may mean the PIXCLK

is not active during the period the

HSYNC and VSYNC signals are

valid.

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