LAN7430 datasheet(55/77 Pages) MICROCHIP

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 2018-2019 Microchip Technology Inc.

DS00002631D-page 55

LAN7430/LAN7431

Note 7-10

Measured at line side of transformer, line replaced by 100

 (+/- 1%) resistor.

Note 7-11

Offset from 16nS pulse width at 50% of pulse peak.

Note 7-12

Peak to Peak, measured differentially.

Note 7-13

Min/max voltages guaranteed as measured with 100

 resistive load.

Note 7-14

Measured differentially following the twisted-pair model with a 100

 resistive load.

Note 7-15

5MHz square wave.

TABLE 7-8:

100BASE-TX TRANSCEIVER CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Notes

Peak Differential Output Voltage

ANSI X3.263 clause 9.1.2.2

VOUT

±0.95

±1.05

Note 7-10

Signal Amplitude Symmetry

ANSI X3.263 clause 9.1.4

VSS

Note 7-10

Signal Rise and Fall Time

ANSI X3.263 clause 9.1.6

TRF

Note 7-10

Rise and Fall Symmetry

ANSI X3.263 clause 9.1.6

TRFS

0.5

Note 7-10

Duty Cycle Distortion

ANSI X3.263 clause 9.1.8

DCD

±0.25

Note 7-11

Overshoot and Undershoot

ANSI X3.263 clause 9.1.3

VOS

Output Jitter

ANSI X3.263 clause 9.1.9

0.7

1.4

Note 7-12

Reference Voltage of ISET (using 6.04kΩ -

1% resistor)

VSET

0.65

TABLE 7-9:

10BASE-T/10BASE-Te TRANSCEIVER CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Notes

Transmitter Peak Differential Output Volt-

age

IEEE 802.3 clause 14.3.1.2.1

VOUT

10BASE-T

2.2

2.5

2.8

Note 7-13

VOUT

10BASE-Te

1.54

1.96

Note 7-13

Output Jitter

IEEE 802.3 clause 14.3.1.2.3

1.8

3.5

Note 7-14

Signal Rise and Fall Time

TRF

Receiver Differential Squelch Threshold

IEEE 802.3 clause 14.3.1.3.2

VDS

300

400

Note 7-15

TABLE 7-10:

PCIe TRANSCEIVER CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Notes

Receiver Input Leakage

(terminations off)

III

2µA

Transmitter Input Leakage

III

µA

PCIe Clock Input Leakage

III

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