LAN7430 datasheet(31/77 Pages) MICROCHIP

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 2018-2019 Microchip Technology Inc.

DS00002631D-page 31

LAN7430/LAN7431

6.0

FUNCTIONAL DESCRIPTIONS

This section provides additional details of the major features supported by the LAN7430/LAN7431.

• PCI Express PHY (PCIe PHY)

• PCI Express Endpoint Controller (PCIe EP)

• Gigabit Ethernet Media Access Controller (MAC)

• RGMII (LAN7431 Only)

• Gigabit Ethernet PHY (GPHY) (LAN7430 Only)

• IEEE 1588v2 (PTP)

• Receive Filtering Engine (RFE)

• DMA Controller (DMAC)

• FIFO Controller (FCT)

• EEPROM Controller (EEP)

• One Time Programmable Memory (OTP)

• Resets

• Power Management

• Integrated Voltage Regulators

• JTAG

• Miscellaneous

6.1

PCI Express PHY (PCIe PHY)

The PCIe PHY forms the physical interface between the device’s PCIe endpoint control and the PCIe host bus. It sup-

ports chip-to-chip and card-to-card connectivity across a combination of printed circuit board, connectors, backplane

wiring or cables.

The PCIe PHY is compliant with all of the required features of the PCIe Base Specification, Revision 3.1 (for legacy 2.5

GT/s support).

The low power L1, L1.1 and L1.2 sub-states are supported per the PCIe Base 3.1 Specification.

6.1.1

FEATURES

• 2.5 GT/s data transmission rate

• PIPE3 compliant Transceiver Interface

• Integrated PHY includes transmitter, receiver, PLL, and digital core

• Programmable RX equalization

• Designed for excellent performance margin and receiver sensitivity

• Low jitter PLL technology with excellent supply isolation

The PHY supports a 2.5 GT/s data rate. Since bytes are encoded using the 8b/10b mechanism, this equates to a 2.0

Gbps data rate.

This device supports a PCIe link width of one lane.

6.1.2

REFERENCE CLOCK

The PHY utilizes an external 100MHz differential reference clock, supplied by the host system. PCIe architecture

defines three clock distribution methods: common clock, data clock, and separate clock. The LAN7430/LAN7431

devices support the common clock method where both end devices, such as a host and the device, are using the same

clock source. The details of the common clock method are provided in the PCIe specification.

6.1.3

TERMINATION RESISTANCE

The PHY includes on chip terminations for the TX and RX I/Os.

Termination on the PCIe reference clock pins is provided by the host.

6.1.3.1

Termination Resistance Tuning

The PHY uses an external resistor to calibrate the termination impedances of the high speed inputs and outputs of the

PHY. A 200 Ohm +/-1% resistor should be connected from the RESREF pin to ground.

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