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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AM6421 bảng dữ liệu(PDF) 174 Page - Texas Instruments |
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AM6421 bảng dữ liệu(HTML) 174 Page - Texas Instruments |
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174 / 237 page  • Legacy speed • High speed SDR • High speed DDR • HS200 Table 7-55 presents the required DLL software configuration settings for MMC0 timing modes. Table 7-55. MMC0 DLL Delay Mapping for All Timing Modes REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG BIT FIELD [31:24] [20] [15:12] [8] [4:0] [17:16] [10:8] [2:0] BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL SELDLYTXCLK SELDLYRXCLK FRQSEL CLKBUFSEL MODE DESCRIPTION STROBE DELAY OUTPUT DELAY ENABLE OUTPUT DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DLL DELAY CHAIN SELECT DLL REF FREQUENCY DELAY BUFFER DURATION Legacy SDR 8-bit PHY operating 1.8 V, 25 MHz 0x0 0x0 NA 0x1 0x10 0x1 0x0 0x7 High Speed SDR 8-bit PHY operating 1.8 V, 50 MHz 0x0 0x0 NA 0x1 0xA 0x1 0x0 0x7 High Speed DDR 8-bit PHY operating 1.8 V, 50 MHz 0x0 0x1 0x6 0x1 0x3 0x0 0x4 0x7 HS200 8-bit PHY operating 1.8 V, 200 MHz 0x0 0x1 0x7 0x1 Tuning 0x0 0x0 0x7 Table 7-56 presents timing conditions for MMC0. Table 7-56. MMC0 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Legacy SDR 0.14 1.44 V/ns High Speed SDR 0.3 0.9 V/ns High Speed DDR (CMD) 0.3 0.9 V/ns High Speed DDR (DAT[7:0]) 0.45 0.9 V/ns OUTPUT CONDITIONS CL Output load capacitance Legacy SDR 1 12 pF High Speed SDR 1 12 pF High Speed DDR 1 12 pF HS200 1 6 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace All modes 126 756 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces Legacy SDR, High Speed SDR 100 ps High Speed DDR, HS200 8 ps 7.10.5.12.1.1 Legacy SDR Mode Table 7-57, Figure 7-57, Table 7-58, and Figure 7-58 present timing requirements and switching characteristics for MMC0 – Legacy SDR Mode. Table 7-57. MMC0 Timing Requirements – Legacy SDR Mode see Figure 7-57 NO. PARAMETER DESCRIPTION MIN MAX UNIT SSDR5 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 9.69 ns SSDR6 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 27.97 ns SSDR7 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge 9.69 ns AM6442, AM6441, AM6421 AM6412, AM6411 SPRSP56 – JANUARY 2021 www.ti.com 174 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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