AM6421 datasheet(92/237 Pages) TI

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6.4 Pin Multiplexing

Note

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins.

Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are

associated with peripheral logic functions.

Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see Pad

Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the device

TRM for information associated with peripheral signal multiplexing.

Note

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

Note

Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the

device TRM.

Note

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal

wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.

For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.

Table 6-77. Pin Multiplexing (ALV Package)

ADDRESS

NAME

BALL

NUMBER

MUXMODE[Bootstrap:0] SETTINGS

Bootstrap

0x000F4000

PADCONFIG

N20

OSPI0_CLK

GPIO0_0

0x000F4004

PADCONFIG

N21

OSPI0_LBCL

GPIO0_1

0x000F4008

PADCONFIG

N19

OSPI0_DQS

GPIO0_2

0x000F400C

PADCONFIG

M19

OSPI0_D0

GPIO0_3

0x000F4010

PADCONFIG

M18

OSPI0_D1

GPIO0_4

0x000F4014

PADCONFIG

M20

OSPI0_D2

GPIO0_5

0x000F4018

PADCONFIG

M21

OSPI0_D3

GPIO0_6

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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