R5F52106ADFN datasheet(4/223 Pages) RENESAS

4 / 223 page

R01DS0041EJ0150 Rev.1.50

Page 4 of 221

Oct 18, 2013

RX210 Group

1. Overview

Timers

16-bit timer pulse unit

(TPUa)

 (16 bits × 6 channels) × 1 unit

 Maximum of 16 pulse-input/output possible

 Select from among seven or eight counter-input clock signals for each channel

 Supports the input capture/output compare function

 Output of PWM waveforms in up to 15 phases in PWM mode

 Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade-

connected operation (32 bits × 2 channels) depending on the channel.

 Capable of generating conversion start triggers for the A/D converters

 Signals from the input capture pins are input via a digital filter

 Clock frequency measuring method

(Products with 144 or more pins incorporate a TPU.)

Multi-function timer pulse

unit 2 (MTU2a)

 (16 bits  6 channels)  1 unit

 Up to 16 pulse-input/output lines and three pulse-input lines are available with six 16-bit timer

channels

 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,

PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than

channel 5, for which only four signals are available.

 Input capture function

 21 output compare/input capture registers

 Pulse output mode

 Complementary PWM output mode

 Reset synchronous PWM mode

 Phase-counting mode

 Generation of triggers for A/D converter conversion

Port output enable 2

(POE2a)

Controls the high-impedance state of the MTU’s waveform output pins

8-bit timer (TMR)

 (8 bits  2 channels)  2 units

 Select from among seven internal clock signals (PCLK1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,

PCLK/1024, PCLK/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

Compare match timer

(CMT)

 (16 bits  2 channels)  2 units

 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Watchdog timer (WDTA)

 14 bits  1 channel

 Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,

PCLK/2048, PCLK/8192)

Independent watchdog

timer (IWDTa)

 14 bits  1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

Frequency divided by 1, 16, 32, 64, 128, or 256

Realtime clock (RTCb)

 Clock source: Sub-clock

 Time/calendar

 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

 Time-capture facility for three values

Table 1.1

Outline of Specifications (3 / 5)

Classification

Module/Function

Description

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