HD404816FS datasheet(14/100 Pages) RENESAS

14 / 100 page

HD404818 Series

$000

112

959

960

1023

$03F

$040

$050

$070

$3FF

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

$00C

$00D

$00E

$00F

$010

$011

$012

$013

$014

$020

$023

$030

$031

$032

$033

$03B

$03C

$03D

$03F

$00A

$00B

$00E

$00F

R/W

$100

$2CF

$3BF

$3C0

$2CF

RAM-mapped registers

Memory registers (MR)

LCD display area (32 digits)

Data (144 digits)

Data (464 digits

V = 0 (bank 0)

V = 1 (bank 1)

Not used

Stack (64 digits)

Interrupt control bits area

Port mode register A

(PMRA)

Serial mode register

(SMR)

Serial data register lower (SRL)

Serial data register upper (SRU)

Timer mode register A

(TMA)

Timer mode register B

(TMB)

Timer B

(TCBL/TLRL)

(TCBU/TLRU)

Miscellaneous register

(MIS)

Timer mode register C

(TMC)

Timer C

(TCCL/TCRL)

(TCCU/TCRU)

Not used

Port mode register B

(PMRB)

LCD control register

(LCR)

LCD mode register

(LMR)

Not used

Port R0 DCR

(DCR0)

Port R1 DCR

(DCR1)

Port R2 DCR

(DCR2)

Port R3 DCR

(DCR3)

Not used

Port D –D DCR

(DCRB)

Port D –D DCR

(DCRC)

Port D –D DCR

(DCRD)

Not used

V register

(V-REG)

Data (464 digits)

V = 1 (bank 1)

Data (464 digits)

V = 0 (bank 0)

Note: Do not use any area labelled "Not used".

Timer counter B lower

(TCBL)

Timer counter B upper

(TCBU)

Timer counter C lower

(TCCL)

Timer counter C upper

(TCCU)

Timer load register B lower

(TLRL)

Timer load register B upper

(TLRU)

Timer load register C lower

(TCRL)

Timer load register C upper

(TCRU)

R/W:

$100

Read only

Write only

Read/write

The data area has two banks:

bank 0 (V = 0) and bank 1 (V = 1)

Figure 2 RAM Memory Map (1,184-digit

× 4-bit)

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