HD404816FS datasheet(87/100 Pages) RENESAS

87 / 100 page

HD404818 Series

Serial Interface Timing Characteristics

During Transmit Clock Output (HD404812, HD404814, HD404816, HD404818: V

CC = 4 to 6 V;

HD4074818: V

CC = 4 to 5.5 V; GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified)

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time t

Scyc

SCK

cyc /

subcyc

1, 2, 4

Transmit clock high and

low widths

SCKH, t SCKL

SCK

0.5

Scyc

1, 2

Transmit clock rise and

fall times

SCKr, t SCKf

SCK

100

1, 2

Serial output data delay

time

DSO

300

1, 2

Serial input data setup

time

SSI

200

Serial input data hold time t

HSI

150

During Transmit Clock Input

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time t

Scyc

SCK

cyc /

subcyc

1, 4

Transmit clock high and

low widths

SCKH, t SCKL

SCK

0.5

Scyc

Transmit clock rise and

fall times

SCKr,

SCKf

SCK

100

Serial output data delay

time

DSO

300

1, 2

Serial input data setup

time

SSI

200

Serial input data hold time t

HSI

150

Transmit clock completion

detect time

SCKHD

SCK

cyc /

subcyc

1,2, 3, 4

Notes: 1. See figure 46.

2. See figure 47.

3. The transmit clock completion detect time is the high level period after 8 pulses of transmit

clocks are input. The serial interrupt request flag is not set if the next transmit clock is input

before the transmit clock completion detect time has passed.

4. The unit t

subcyc is applied when the MCU is in subactive mode.

subcyc = 244.14 µs (for a 32.768-

kHz crystal oscillator).

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