PCF8536AT datasheet(34/54 Pages) NXP

34 / 54 page

PCA85233

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Product data sheet

Rev. 5 — 12 November 2018

34 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

[1]

Typical output duty cycle of 50 %.

[2]

The corresponding frame frequency is

[3]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD. For I2C-bus timings see Figure 24.

Pins SCL and SDA

tBUF

bus free time between a

STOP and START

condition

1.3

s

tSU;STO

set-up time for STOP

condition

0.6

s

tHD;STA

hold time (repeated)

START condition

0.6

s

tSU;STA

set-up time for a repeated

START condition

0.6

s

rise time of both SDA and

SCL signals

fSCL = 400 kHz

0.3

s

fSCL < 125 kHz

1.0

s

fall time of both SDA and

SCL signals

0.3

s

capacitive load for each

bus line

400

tw(spike)

spike pulse width

on bus

Table 21.

Dynamic characteristics …continued

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

clk

--------

(1) VDD =5.5 V; FF =VSS.

(2) VDD =5.5 V; FF =VDD.

(3) VDD =1.8 V; FF =VSS.

(4) VDD =1.8 V; FF =VDD.

Fig 22. Frame frequency with respect to temperature

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