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PCF8536AT bảng dữ liệu(PDF) 25 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  Automotive 80 횞 4 LCD driver for low multiplex rates
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PCF8536AT bảng dữ liệu(HTML) 25 Page - NXP Semiconductors

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PCA85233
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 5 — 12 November 2018
25 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
The START and STOP conditions are shown in Figure 15.
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 16.
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 17.
Fig 15. Definition of START and STOP conditions
Fig 16. System configuration



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