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ADL9006ACGZN-R7 bảng dữ liệu(PDF) 13 Page - Analog Devices |
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ADL9006ACGZN-R7 bảng dữ liệu(HTML) 13 Page - Analog Devices |
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13 / 14 page ![]() Data Sheet ADL9006 Rev. 0 | Page 13 of 14 APPLICATIONS INFORMATION BIASING PROCEDURES Capacitive bypassing is required for VDD, as shown in the typical application circuit in Figure 38. Gain control is possible through the application of a dc voltage to the VGG2 pin. If gain control is used, VGG2 must be bypassed by a 100 pF capacitor, a 0.01 μF capacitor, and a 4.7 μF capacitor. If gain control is not used, VGG2 can be either left open or capacitively bypassed, as shown in Figure 38. The recommended bias sequence during power-up is as follows: 1. Set VDD to 5 V (this setting results in an IDD near its specified typical value). 2. If the gain control function is used, apply a voltage within the range of −2.0 V to +2.6 V to VGG2 until the desired gain is achieved. 3. Apply the RF input signal. The recommended bias sequence during power-down is as follows: 1. Turn off the RF input signal. 2. Remove the VGG2 voltage or set it to 0 V. 3. Set VDD to 0 V. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit (see Figure 38), biased per the conditions in the Specifications section. The bias con- ditions shown in the Specifications section are the operating points recommended to optimize the overall performance of the device. Operation using other bias conditions may provide performance that differs from what is shown in this data sheet. To obtain the optimal performance while not damaging the device, follow the recommended biasing sequences outlined in this section. VGG2 RFIN RFOUT VDD 0.01µF 100pF 4.7µF 0.01µF 100pF 4.7µF 2 31 21 4 Figure 38. Typical Application Circuit |
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