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FS32K112MHTXMLUTR bảng dữ liệu(PDF) 48 Page - NXP Semiconductors |
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FS32K112MHTXMLUTR bảng dữ liệu(HTML) 48 Page - NXP Semiconductors |
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48 / 100 page  Table 37. Flash command timing specifications for S32K11x series (continued) Symbol Description1 S32K116 S32K118 Typ Max Typ Max Unit Notes 48 KB EEPROM backup — — — — 64 KB EEPROM backup — — — — teewr8b Byte write to FlexRAM execution time 32 KB EEPROM backup 385 1700 385 1700 µs 3,4 48 KB EEPROM backup — — — — 64 KB EEPROM backup — — — — teewr16b 16-bit write to FlexRAM execution time 32 KB EEPROM backup 385 1700 385 1700 µs 3,4 48 KB EEPROM backup — — — — 64 KB EEPROM backup — — — — teewr32bers 32-bit write to erased FlexRAM location execution time — 360 2000 360 2000 µs teewr32b 32-bit write to FlexRAM execution time 32 KB EEPROM backup 630 2000 630 2000 µs 3,4 48 KB EEPROM backup — — — — 64 KB EEPROM backup — — — — tquickwr 32-bit Quick Write execution time: Time from CCIF clearing (start the write) until CCIF setting (32-bit write complete, ready for next 32-bit write) 1st 32-bit write 200 550 200 550 µs 4,5,6 2nd through Next to Last (Nth-1) 32-bit write 150 550 150 550 Last (Nth) 32-bit write (time for write only, not cleanup) 200 550 200 550 tquickwrClnup Quick Write Cleanup execution time — — (# of Quick Writes ) * 2.0 — (# of Quick Writes ) * 2.0 ms 7 1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external clocks). 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM issues detected. 4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2x the times shown. 5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record set will still be valid and the new records will be discarded. Memory and memory interfaces S32K1xx Data Sheet, Rev. 12, 02/2020 48 NXP Semiconductors |
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