FS32K112MHTXMLLTR datasheet(87/100 Pages) NXP

87 / 100 page

Table 55. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package

(continued)

Rating

Conditions

Symbol

Package

Values (in °C/W)

S32K116 S32K118 S32K142

S32K142

S32K144

S32K146 S32K148

176

Thermal resistance, Junction to

Package Top7

Natural

Convection

ψJT

100

144

176

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air

flow, power dissipation of other components on the board, and board thermal resistance.

Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.

Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the

package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek

letters are not available, the thermal characterization parameter is written as Psi-JT.

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