FS32K112MHTXMLLTR datasheet(55/100 Pages) NXP

55 / 100 page

Table 40. 12-bit ADC operating conditions

Symbol

Description

Conditions

Min.

Typ.1

Max.

Unit

Notes

S32K1xx/

S32K14xW

S32K1xx/

S32K14xW

S32K1xx

S32K14xW

VREFH

ADC reference voltage high

See Voltage

and current

operating

requirements

for values

VDDA

See Voltage and current

operating requirements for

values

VREFL

ADC reference voltage low

See Voltage

and current

operating

requirements

for values

See Voltage and current

operating requirements for

values

VADIN

Input voltage

VREFL

—

VREFH

Source impedendance

fADCK < 4 MHz

—

kΩ

RSW1

Channel Selection Switch Impedance

—

0.75

1.2

kΩ

RAD

Sampling Switch Impedance

—

kΩ

CP1

Pin Capacitance

—

CP2

Analog Bus Capacitance

—

Sampling capacitance

—

fADCK

ADC conversion clock frequency

Normal usage

MHz

3, 4

fCONV

ADC conversion frequency

No ADC hardware averaging.5

Continuous conversions

enabled, subsequent conversion

time

46.4

928

1160

Ksps

6, 7

ADC hardware averaging set to

32. 5 Continuous conversions

enabled, subsequent conversion

time

1.45

36.25

Ksps

6, 7

Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and

are not tested in production.

For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference

supply quality should be better than SAR ADC. See application note AN5032 for details.

Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .

ADC conversion will become less reliable above maximum frequency.

When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.

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