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Table 8. VDD supply LVR, LVD and POR operating requirements for S32K1xx series
(continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VLVW
Falling low-voltage warning threshold
4.19
4.305
4.5
V
VLVW_HYST
LVW hysteresis
—
75
—
mV
1
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
Table 9. VDD supply LVR, LVD and POR operating requirements for S32K14xW series
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Rising and falling VDD POR detect voltage
1.1
1.6
2.0
V
VLVR
LVR falling threshold (RUN and STOP
modes)
2.97
3.02
3.07
V
VLVR_HYST
LVR hysteresis
—
45
—
mV
1
VLVR_LP2
LVR falling threshold (VLPS/VLPR modes)
2.06
2.26
2.46
V
VLVW
Falling low-voltage warning threshold
4.19
4.305
4.5
V
VLVW_HYST
LVW hysteresis
—
75
—
mV
1
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
2. An internal monitor could reset the chip at a higher supply level, but 3.13 V onward the chip is fully functional.
4.6 Power mode transition operating behaviors
All specifications in the following table assume this clock configuration:
Table 10. Clock configuration
S32K1xx
S32K14xW
RUN mode
Clock source
FIRC
FIRC
SYS_CLK/CORE_CLK
48 MHz
48 MHz
BUS_CLK
48 MHz
48 MHz
FLASH_CLK
24 MHz
16 MHz
HRUN mode
Clock source
SPLL
NA
SYS_CLK/CORE_CLK
112 MHz
NA
BUS_CLK
56 MHz
NA
FLASH_CLK
28 MHz
NA
VLPR mode
Clock source
SIRC
SIRC
Table continues on the next page...
General
S32K1xx Data Sheet, Rev. 12, 02/2020
18
NXP Semiconductors



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