MXT1664T3-C2TESSQTP datasheet(27/98 Pages) MICROCHIP

27 / 98 page

MXT1664T3 2.0

 2018 Microchip Technology Inc.

DS40002054A-page 27

FIGURE 5-2:

POWER SEQUENCING ON THE MXT1664T3 – LATE RISE ON AVDD OR XVDD

The RESET pin can be used to reset the device whenever necessary. The RESET pin must be asserted low for at least

90 ns to cause a reset. After releasing the RESET pin the device typically takes 81 ms before it is ready to start

communications. It is recommended to connect the RESET pin to a host controller to allow it to initiate a full hardware

reset without requiring a power-down.

Make sure that any lines connected to the device are below or equal to Vdd during power-up. For example, if RESET

is supplied from a different power domain to the VDDIO pin, make sure that it is held low when Vdd is off. If this is not

done, the RESET signal could parasitically couple power via the RESET pin into the Vdd supply.

A software RESET command (using the Command Processor T6 object) can be used to reset the chip. A software reset

typically takes 104 ms. After the chip has finished it asserts the CHG line to signal to the host that a message is

available. The reset flag is set in the Command Processor T6 object message data to indicate to the host that it has just

completed a reset cycle. This bit can be used by the host to detect any unexpected brownout events. This allows the

host to take any necessary corrective actions, such as reconfiguration.

At power-on, the device performs a self-test routine (using the Self Test T25 object) to check for shorts that might cause

damage to the device.

5.2

Power-up and Reset Sequence – VddIO Enabled after Vdd

The power-up sequence that can be used in applications where VddIO must be powered up after Vdd, is shown in

Figure 5-3 on page 28.

In this case the communication interface to the maXTouch device is not driven by the host system. The RESET and

CHG pins are connected to VddIO using suitable pull-up resistors. Vdd is powered up, followed by VddIO, no more than

10 ms after Vdd. Due to the pull-up resistors, RESET and CHG will rise with VddIO. The internal POR system ensures

reliable boot up of the device and the CHG line will go low approximately 79 ms after Vdd to notify the host that the

device is ready to start communication.

WARNING

The device should be reset only by using the RESET line. If an attempt is made to reset by removing

the power from the device without also sending the signal lines low, power will be drawn from the

interface lines and the device will not reset correctly.

NOTE

The voltage level on the RESET pin of the device must never exceed VddIO (digital supply voltage).

NOTE

The CHG line is briefly set (~100 ms) as an input during power-up or reset. It is therefore particularly

important that the line should be allowed to float high via the CHG line pull-up resistor during this period.

It should never be driven by the host (see Section 14.7.3 “Reset Timings”).

(Nom)

AVdd or

XVdd

(Nom)

Vdd/VddIO

(VddIO)

RESET

RESET deasserted before AVdd/XVdd at

nominal level

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