2EDF7275K datasheet(7/38 Pages) INFINEON

7 / 38 page

Final datasheet

Rev.2.5

2020-03-17

EiceDRIVER™ 2EDi product family

2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers

Pin configurations by device type

For package drawing details see Chapter 7 Package outline dimensions.

Table 2

Pin description for dual-channel input mode (with DISABLE, SLDON)

Pin#

DSO

Pin#

LGA

Symbol Description

INA

Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to

GNDI

If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)

INB

Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to

GNDI

If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4)

VDDI

Supply voltage (input side) 3.3 V (Internal SLDO available)

It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1)

GNDI

Ground input side (all signals on input side are referenced to this pin)

(see Chapter 3.3.1)

DISABLE Digital CMOS / TTL logic input for both channels A and B; logic input high disables both

output channels

Internal pull-down resistor (see Chapter 3.4)

N.C.

Not connected; keep pin floating

N.C.

Not connected; keep pin floating

SLDON

Default 3.3 V supply selected, if N.C. or connected to VDDI

If SLDON pin is connected to GNDI, SLDO is activated and a supply voltage higher than

3.5 V can be used (see Chapter 3.3.1)

Internal pull-up resistor to VDDI; hard-wired PCB connection recommended

GNDB

Ground for output channel B

OUTB

Output gate driver for channel B

10 VDDB

Supply voltage for output channel B

It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2)

12 N.P. N.C.

Not present; not connected; for channel-to-channel isolation

N.C.

Not connected; for channel-to-channel isolation

11 GNDA

Ground for output channel A

12 OUTA

Output gate driver for channel A

13 VDDA

Supply voltage for output channel A

It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2)

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