XRT7250 datasheet(164/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

145

Mode 5 Operation of the Terminal Equipment

In Figure 52 both the Terminal Equipment and the

XRT7250 will be driven by an external 11.184MHz

clock signal. The Terminal Equipment will receive the

11.184MHz clock signal via the DS3_Nib_Clock_In

input pin. The XRT7250 will output the 11.184MHz

clock signal via the TxNibClk output pin.

The Terminal Equipment will serially output the data

on the DS3_Data_Out[3:0] pins, upon the rising edge

of the signal at the DS3_Clock_In input pin.

NOTE: The DS3_Data_Out[3:0] output pins of the Terminal

Equipment is electrically connected to the TxNib[3:0] input

pins.

The XRT7250 will latch the data, residing on the Tx-

Nib[3:0] input pins, on the rising edge of the TxNibClk

signal.

In this case, the Terminal Equipment has the respon-

sibility of providing the framing reference signal by

pulsing the Tx_Start_of_Frame output pin (and in

turn, the TxFrameRef input pin of the XRT7250)

"High" for one bit-period, coincident with the first nib-

ble of a new DS3 frame. Once the XRT7250 detects

the rising edge of the input at its TxFrameRef input

pin, it will begin generation of a new DS3 frame.

Finally, the XRT7250 will always internally generate

the Overhead bits, when it is operating in both the

DS3 and Nibble-parallel modes. The XRT7250 will

pull the TxOHInd input pin "Low".

The behavior of the signals between the XRT7250

and the Terminal Equipment for DS3 Mode 5 Opera-

tion is illustrated in Figure 53.

FIGURE 52. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA

INPUT INTERFACE BLOCK OF THE XRT7250 FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-SLAVE) OPERA-

TION

Terminal Equipment

XRT7250 DS3 Framer

DS3_Data_Out[3:0]

DS3_Nib_Clock_In

Tx_Start_of_Frame

TxNib[3:0]

TxNibClk

TxFrameRef

NibInt

VCC

44.736MHz Clock Source

TxInClk

11.184MHz

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