CDCE6214RGET datasheet(7/53 Pages) TI1

7 / 53 page

CDCE6214

www.ti.com

SNAS811 – JULY 2020

Product Folder Links: CDCE6214

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General-Purpose Input Characteristics (continued)

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIL

Input low level current

VIL = GND, GPIO[2:3]

-5

µA

IIL

Input low level current

VIL = GND, GPIO[1], GPIO[4], PDN

-100

100

µA

dVIN/dT

Input slew rate

20% - 80%

0.5

V/ns

TPULSE_WIDT

Pulse width for correct operation

RPU

Pullup Resistance

Pins PDN, GPIO[1], GPIO[4]

Ω

CIN

Pin Capacitance

7.10 Triple Level Input Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIH

Input high voltage

0.8 ×

VDD_REF

VIM

Input mid voltage

Float pin

0.41 ×

VDD_REF

0.5 ×

VDD_REF

0.58 ×

VDD_REF

VIL

Input low voltage

0.2 ×

VDD_REF

IIH

Input high level current

VIH = VDD_REF

100

µA

IIL

Input low level current

VIL = GND

-100

-50

-20

µA

7.11 Logic Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

Output high voltage

0.8 ×

VDD_REF

VOL

Output low voltage

0.2 ×

VDD_REF

(1)

The maximum allowable temperature drift for continuous lock: how far the temperature can drift in either direction from the value it was

at the time, when the On-Chip VCO was calibrated while the PLL stays in lock throughout the temperature drift. The internal VCO

calibration takes place: at device start-up, when the device is reset using the RESET pin and when REGISTER bit is changed. This

implies the device will work over the entire frequency range, but if the temperature drifts more than the 'maximum allowable temperature

drift for continuous lock', then it is necessary to re-calibrate the VCO, using the appropriate REGISTER bit, to ensure the PLL stays in

lock. Regardless of what temperature the part was initially calibrated at, the temperature can never drift outside the ambient temperature

range of -40° C to 105° C.

7.12 Phase Locked Loop Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fPFD

Phase Detector Frequency

Integer and Fractional PLL mode

100

MHz

fVCO

Voltage Controlled Oscillator Frequency

2335

2625

MHz

fBW

Configurable closed-loop PLL Bandwidth

REF = 25 MHz

100

1600

kHz

KVCO

Voltage-Controlled Oscillator Gain

fVCO = 2.4 GHz

140

MHz/V

KVCO

Voltage-Controlled Oscillator Gain

fVCO = 2.5 GHz

175

MHz/V

|ΔTCL|

Allowable Temperature Drift for

Continuous Lock(1)

dT/dt

≤ 20 K / min

145

fMAX-ERROR

Maximum frequency error with frac-N PLL

0.1

ppm

7.13 Closed-Loop Output Jitter Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tRJ_CL

RMS Phase Jitter

RMS jitter with spurs from 12 kHz to 20

MHz , Input Crystal = 25 MHz, Differential

OUTx > 100 MHz, int-PLL

350

600

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