CDCE6214RGET datasheet(21/53 Pages) TI1

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CDCE6214

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SNAS811 – JULY 2020

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9.3.2 Phase-Locked Loop (PLL)

The CDCE6214 has a fully-integrated Phase-Locked Loop (PLL) circuit. The error between a reference phase

and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a

charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes

an internal Voltage-Controlled Oscillator (VCO). The frequency of the VCO is fed through a feedback divider (N-

counter) back to the PFD.

•

Integer and Fractional-N PLL mode of operation.

•

First-, Second-, or Third-Order MASH operation in Fractional mode.

•

24-bit Numerator and Denominator can be used to generate fractional frequencies with 0 ppb frequency

accuracy.

•

PFD operates between 1 MHz and 100 MHz.

•

Live Lock Detector (R7[0] or PLL_LOCK in GPIO) provides PLL Lock status (in fractional mode and SSC

enabled, lock detect window need to be widened. R50[10:8] = 7h). Additionally, sticky bit lock detect (R7[1])

detects if there was any temporary loss of lock.

•

Integrated selectable loop filter components.

•

For a 25-MHz PFD frequency, PFD bandwidth between 100 kHz and 1.6 MHz can be achieved to optimize

PLL to input reference.

•

Voltage-controlled oscillator (VCO) ranges from 2335 MHz to 2615 MHz.

•

Supports 0.25% and 0.5% center and down spread Spread Spectrum Clocking (SSC) generation. Further,

VCO also supports up to 0.5% SSC references at 100 MHz for PCIe clocking.

Table 3. Common Clock Generator Loop Filter Settings

fVCO IN MHz

fPFD IN MHz

BW IN MHz

PHASE

MARGIN IN °

DAMPING

FACTOR

ICP IN mA

CPcap IN pF

RRes IN kΩ

CZcap IN pF

2400

0.469

0.5

0.60

16.1

2.5

580

2400

0.938

0.60

8.2

2.5

276

2400

100

1.60

0.5

0.80

8.2

2.5

303

2457.6

61.44

1.04

1.15

0.60

9.2

2.0

331

2500

0.49

0.4

0.60

13.5

2.5

497

2500

0.93

1.0

0.60

11.7

2.5

386

2400

400

0.1

0.40

11.7

1.5

636

(1)

Fractional Mode settings are based on DCO mode step size of 0.1ppm

Table 4. Common PLL Divider Settings (1)

INPUT

FREQUENCY

IN MHz

fPFD IN MHz

OUTPUT

FREQUENCY

IN MHz

fVCO

N-COUNTER

DIVIDER VALUE

NUMERATOR

DENOMINATOR

PSA

OUTPUT

DIVIDER

100

2400

100

2400

156.25

2500

2400

24.576

2457.6

5071614

16682942

148.5

2376

664983

16624579

9.3.2.1 PLL Configuration and Divider Settings

fPFD= Fin/Ffactor

Ffactor is determined by R25[7:0] - ip_ref_div. Ffactor = 0.5 when ip_ref_div=0, Ffactor = ip_ref_div, otherwise.

fVCO = fPFD × (N + Num/Den).

N is set by R30[14:0] - PLL_NDIV. Num is the numerator of the fraction, set by {R32[7:0],R31[15:0]}. Den is the

denominator of the fraction, set by R34[7:0],R33[15:0]. When {R34[7:0],R33[15:0]} = 0, Den=224.

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