CDCE6214RGET datasheet(29/53 Pages) TI1

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CDCE6214

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SNAS811 – JULY 2020

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9.3.4 Power Supplies and Power Management

The CDCE6214 provides multiple power supply pins. Each of the power supplies supports 1.8 V, 2.5 V, or 3.3 V

individually. Internal low-dropout regulators (LDO) source the internal blocks and allow each pin to be supplied

with its individual supply voltage. The VDDREF pin supplies the control pins and the serial interface, therefore

any pullup resistors shall be connected to the same domain as VDDREF.

The device is very flexible with respect to internal power management. Each block offers a power-down bit and

can be disabled to save power when the block is not required. The available bits are illustrated in Table 15. The

bypass output Y0 is connected to the pdn_ch4 bit. Each output channel has a bit which should be adapted to the

applied supply voltage, ch[4:1]_1p8vdet.

Table 15. Power Management

VDDREF

VDDVCO

VDDO_12

VDDO_34

R0[1] - POWERDOWN

R5[8] - PLL_VCOBUFF_LDO_PD

R4[4] - CH1_PD

R4[6] - CH3_PD

R5[7] - PLL_VCO_LDO_PD

R4[5] - CH2_PD

R4[7] - CH4_PD

R5[6] - PLL_VCO_BUFF_PD

R5[5] - PLL_CP_LDO_PD

R5[4] - PLL_LOCKDET_PD

R5[3] - PLL_PSB_PD

R5[2] - PLL_PSA_PD

R5[1] - PLL_PFD_PD

R53[6] - PLL_NCTR_EN

R53[3] - PLL_CP_EN

9.3.5 Control Pins

The ultra-low power clock generator is controlled by multiple LVCMOS input pins.

HW_SW_CTRL pin acts as EEPROM page select. The CDCE6214 clock generator contains two pages of

configuration settings. The level of this pin is sampled after device power up. A low level selects page zero. A

high level selects page one. The HW_SW_CTRL pin is a tri-level input pin. This third voltage level is

automatically applied by an internal voltage divider. The mid-level is used to select an internal default where the

serial interface is enabled.

PDN/SYNCN (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-

purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be

active.

PDN/SYNCN resets the internal circuitry and is used in the initial power-up sequence. The pin can be

reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNCN is low. When

SYNCN is high, outputs are active.

Table 16. Control and GPIO Pins

PIN NO.

NAME

TYPE

2-LEVEL INPUT

3-LEVEL INPUT

OUTPUT

TERMINATION

HW_SW_CTRL

Input

Yes

PUPD

GPIO1

Input/Output

Yes

PU (when Input)

GPIO2

Input/Output

Yes

Open-Drain I/O in

I2C mode, CMOS

(Input)

GPIO3

Input

Yes

GPIO4

Input/Output

Yes

PU (when Input)

PDN

Input

Yes

PU (when Input)

REFSEL

Input

Yes

PUPD

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